1. Background of the Invention
The invention relates generally to stacked microelectronic modules. Specifically, the invention relates to a device comprised of stacked integrated circuit (IC) package layers, such as ball grid array packages (BGA) or flip chip bonded IC chip layers that are interconnected to an external circuit by means of an interposer layer and an interface printed circuit board (PCB).
In the microelectronics industry, there are significant advantages to stacking and interconnecting commercial off the shelf (COTS) integrated circuit packages. The primary advantage of stacking layers is maximum utilization of limited surface area on a printed circuit board. Vertically stacking integrated circuit packages provides increased circuit density without requiring additional printed circuit board space. Further, stacking integrated circuit packages reduces signal lead lengths between the stacked components, reducing parasitic inductance and capacitance, which in turn, allows the circuits to operate at very high clock speeds. The use of COTS components also provides the advantage of ensuring the stack contains fully burned in, tested and functional die, i.e., ensures the use of known good die (KGD) in the stack.
Industry has recognized the value of stacking COTS integrated circuits as is reflected in U.S. Pat. Nos. 6,026,352 to Eide, 6,806,559 to Gann, and 6,706,971, to Albert, all to common assignee, Irvine Sensors Corp. and each of which is incorporated fully herein by reference.
The current microelectronic packaging trend is toward ball grid array packages which comprise an array of solder ball interconnections for I/O to and from the internal integrated circuit die on the lower surface of the BGA package. The solder balls are reflowed on a registered set of conductive pads on an external circuit for interconnection therewith. It is therefore desirable to provide a device that takes advantage of the benefits of stacking and that can accommodate ball grid array packages or other layers that comprise an array of registered I/O pads for interconnection, which device can be adapted for use on a standard BGA printed circuit board pattern.
2. Brief Summary of the Invention
The present invention discloses a device and method comprising a stack of at least two IC package layers, such as ball grid array packages, stacked with an interposer layer. The solder balls of an upper, or first, IC package layer are in electrical connection with a registered set of conductive pads on a surface of the interposer layer. The interposer layer comprises one or more conductive traces for the rerouting of an electrical signal to the appropriate location in the stack and includes one or more angularly depending leads for interconnection with an interface PCB.
The solder balls of a lower, or second, IC package are in electrical interconnection with a registered set of conductive pads on the interface PCB. The interface PCB comprises one or more interface PCB conductive traces on a substrate for the rerouting of electrical signals to or from an external circuit to the appropriate layers in the stack.
In the above manner, multiple pretested BGA packages containing known good die can be efficiently stacked and interconnected in a reliable, low cost microelectronic module.
While the claimed IC layer apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 USC 112, are not to be construed as necessarily limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 USC 112, are to be accorded full statutory equivalents under 35 USC 112.
The invention and its various embodiments can now be better understood by turning to the following detailed description of the preferred embodiments which are presented as illustrated examples of the invention defined in the claims. It is expressly understood that the invention as defined by the claims may be broader than the illustrated embodiments described below.